[center]Last updated 7/2021
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 752.05 MB | Duration: 1h 15m

FPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP[/center]

What you'll learn
FPGA flow vs ASIC flow
Basic mixed-signal RISC-V based SoC RTL design and simulations
FPGA Synthesis, bit-stream generation and simulation
Requirements
VSD - RISC-V ISA course on Udemy
VSD - Pipelining RISC-V using TL-Verilog course on Udemy
Description
This webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to verilog language and is a part of a mixed-signal SoCIf you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferredThis single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verificationStay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board. Innovation at its best All the best and happy learning
Overview
Section 1: Introduction
Lecture 1 Introduction
Section 2: Mixed Signal SoC details with RISC-V core and PLL IP
Lecture 2 RVMYTH RISC-V Core
Lecture 3 Transaction level Verilog
Lecture 4 Why FPGAs ?
Lecture 5 Makerchip platform
Lecture 6 TL - Verilog to RTL verilog
Lecture 7 Functional Simulation using iverilog
Section 3: Mixed Signal FPGA flow
Lecture 8 FPGA - Steps to create project
Lecture 9 FPGA - Steps to generate IPs
Lecture 10 FPGA - RTL simulation
Lecture 11 FPGA - Synthesis
Lecture 12 FPGA - Implementation and timing analysis
Lecture 13 FPGA - Bit-stream generation, FPGA programming and ILA
Section 4: Conclusion
Lecture 14 Conclusion and Assignment
Beginner in FPGA design,Beginner in VLSI design,Experienced Physical Design and STA engineers

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