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SDAccel is an OpenCL programming system, C / C ++ for heterogeneous systems with the implementation of hardware accelerators on Xilinx FPGA. OpenCL is one of the applications of the C ++ language for the development of FPGA firmware. SDAccel supports any combination of OpenCL, C, and C ++ cores with libraries for FPGA design. This environment allows parallel programming of both the central processor and FPGA accelerators.
SDSoC development environment is intended only for Zynq (this is a chip in which there is a FPGA and an AWP processor in one package).

Add. Information : Starting with version 2016.3, SDAccel and SDSoC combined into one package called SDx. SDSoC works in Windows and Linux. SDAccel only works under some versions of Linux.
SDSoC and SDAccel are characterized by the fact that the FPGA project already fades into the background. In the foreground - the algorithm. Both systems allow modeling at the level of the original algorithm written in C / C ++ and then translate it to FPGA. This allows you to dramatically increase the complexity of the algorithm.
If we compare the programming for the FPGA on VHDL / Verilog and on C / C ++, then it begs the analogy between programming for conventional processors in C / C ++ and assembler. In an assembler, you can make a more compact and fast code, and in C / C ++ you can write a more complex program.

Details:
Xilinx SDAccel/SDSoC 2018.2
Year/Date of Release:2018
Version:2018.2
Developer:Xilinx Inc.
Architecture:64bit
Language:English
Medicine:Present

System Requirements:

System requirements SDAccel:
The presence of one of the accelerators:
-the Xilinx Kintex UltraScale KCU1500 the FPGA Reconfigurable Acceleration card based on XCKU115-FLVB2104-2 the FPGA-E,
-the Xilinx the Virtex UltraScale + VCU1525 the FPGA Reconfigurable Acceleration card based on XCVU9P-L2FSGD2104E FPGA.
-Host computer for an accelerator with the characteristics Mat.
-card with support for PCIe Gen3 X8 slot,64GB OP,
-Disk:100 GB of free hard disk space.

Computer for programming:
PC with installed environment Vivado Design Suite 2018.2 and Xilinx Platform Cable USB 2 (HW-USB-II-G).
OS Red Hat Enterprise Workstation / Server 7.3-7.4 (64-bit), CentOS 7.2, Ubuntu Linux 16.04.3 LTS (64-bit)

SDSoC system requirements:
One of the following developer platforms:
-ZC702, ZC706, ZedBoard based on Zynq- 7000 SoC,
-ZCU102, ZCU104, ZCU106 based on Zynq UltraScale + MPSoC.
For Windows version: Microsoft Windows 7 / 8.x / 10 Professional (64-bit)
For Linux version: Red Hat Enterprise Workstation OS 6.7 / 6.8, Red Hat Enterprise Workstation Server / Server 7.3-7.4 (64-bit), CentOS 7.2 / 7.3 / 7.4 (64-bit), Ubuntu Linux 16.04.3 LTS (64-bit )

WHATS NEW:
SDAccel Development Environment What's New for 2018.2:

The following SDAccel™ Development Environment updates are included in the 2018.2 release.

-Ease-of-Use enhancements to simplify Project Management.
-A one-stop SDx™ IDE Assistant from which to drive all flows and actions.
-Actionable Guidance with improved Reporting and visualization.
-Introduction of transaction-level hardware Debug.
-runtime enhancements that allow applications to execute faster and with less memory.
-Additional options for Platform and RTL Kernels are provided.

Note: New updates to the HLS Compiler for 2018.2 are also provided below.
Supported Platforms

For a list of all supported platforms and devices, see the SDAccel Product Page.
Project Management

-Seamless and direct access to the HLS compiler is now provided from within the SDx GUI.
-The Vivado® HLS Compiler may be launched directly on any kernel, allowing detailed analysis and optimization to be performed within the HLS compiler environment. All changes are automatically saved into the SDx project when exiting the HLS Compiler.
-Improvements to the SDx project directory structure allows for easier access to report and log files.
-Ability to export and import a project to move between workspaces. This includes custom build/debug configurations
-Prior releases had one project for Vivado synthesis and a second for Vivado implementation. Now there is a single project with both synthesis and implementation for easier debug flow.

SDx IDE:
-New SDx Assistant view to manage SDx software projects. The view is used to manage hardware functions, build projects, and view reports. Common actions are in a pop-up menu for ease of use.
-New tabs in Debug Perspective to display contents of OpenCL™ Command Queues, Memory Buffers, Monitors and Protocol Checkers.

Reporting:
-The new Guidance feature provides actionable feedback, enabling users to more easily optimize for performance.
-Online Guidance is augmented with new documentation guides, including a Programmers Guide, Profiling and Optimization Guide and a Verification and Debug Guide.
-Profile Summary enhanced to report compute unit stalls and execution monitoring.
-Compiler and Linker Options enhanced to control granularity of profile counter and trace data collection, monitor and report compute unit stalls, and execution of compute units

-Application Timeline View enhanced to provide more visibility into kernel operations, enabling faster identification and optimization of performance bottlenecks.
-Reporting of compute unit port level transfers, NDRange Start/Stop Time, and event dependencies.
-Display of function level activity within a compute unit.
-New reporting features allow dynamically trading off SDAccel execution-time versus detailed reporting.
-Detailed, but time consuming, hardware level reports are no longer generated by default but are available through the GUI and xocc command options.

Debug:
-xocc provides a new switch, --dk chipscope for users familiar with the FPGA design flow to compile their application and get transaction level visibility when running on hardware.

Runtime:
-Applications now execute faster and using less memory with runtime management now implemented in dedicated hardware.

Platform and RTL Kernels:
-Optional Reset for RTL Kernels to improve timing closure.
-The Feature ROM is enhanced to include information on the DSA Power Monitoring, Scheduler, and Debugging.

HLS Compiler
-New Schedule Viewer accessible from the Analysis Perspective to graphically display dependencies of operations and control steps.
-Overall faster processing of source code embedded directives (pragmas).
-Redesigned "dataflow" with strict-mode checks to help guide toward optimal solution.
-Performance enhancements with both higher clock rates (4% higher on average) and reduced design latency with 10% fewer clock cycles for design completion.
-Five additional math.h optimized functions for fixed-point data types (pow, abs, sincos, acos, asin).
-XFast xfOpenCV libraries are now fully supported in Vivado HLS.
-Co-simulation waveforms are enhanced to clearly display DATAFLOW transaction views.
-New DRCs added to the Vivado HLS GUI DRC tab to expedite timing closure and strengthen pragma checks.

SDSoC Development Environment What's New for 2018.2:

The following updates to the SDSoC™ Development Environment are included in the 2018.2 release:

-New Platforms and faster clocks deliver performance improvements.
-SDx™ IDE enhancements that include an Assistant, actionable Guidance, and simplified import/export.
-Ease-of-Use improvements for C-Callable IP that simplify and protect IP libraries.
-Introduction of transaction-level hardware Debug.

Note: New updates to the HLS Compiler for 2018.2 are also provided below.
Supported Platforms

For a list of all supported platforms and devices, see the SDSoC Product Page.

-Support for two new platforms, ZCU104 and ZCU106, giving more choice in base hardware.
-To ease custom platform creation, there is now a Platform Interfaces Tab in Vivado® IP Integrator that can be used for setting SDSoC™ platform properties.
-Faster clock for data movers. The system compiler now puts the HW accelerator and the data mover on the same clock for faster data transfers and system performance.

SDx IDE:
-Assistant.
-New view to manage SDx software projects. This view is used to manage hardware functions, build projects, and view reports. The common actions are in the pop-up menu for ease of use.
-Project Export/ Import.
-Gives ability export and import a project to move between workspaces. This includes custom build/debug configurations.
-Guidance on Linux (only for the HLS portion of the flow).
-Provides feedback on the coding styles in the accelerator from the HLS tools.

C-Callable IP:
-Changes to the flow to make it easier to create and use a library of C-Callable IP.
-Third party IP providers are allowed to encrypt IP, enabling an IP market.
-SDx_pack replaces the harder to use sdslib.

Debug:
-sds++ has a new switch, --dk, for users familiar with the FPGA design flow. This switch allows them to compile their application to get transaction level visibility when running on hardware.
-Prior releases had one project for Vivado synthesis and a second for Vivado implementation. Now there is a single project with both synthesis and implementation and improved debug flow.

HLS Compiler:
-A new Schedule Viewer accessible from the Analysis Perspective graphically displays dependencies of operations and control steps.
-Overall faster processing of source code embedded directives (pragmas).
-Redesigned "dataflow" with strict-flow checks to help guide toward optimal solution.
-Performance enhancements with both higher clock rates (4% higher on average) and reduced design latency with 10% fewer clock cycles for design completion.
-Five additional math.h optimized functions for fixed-point data types (pow, abs, sincos, acos, asin).
-XFast xfOpenCV libraries are now fully supported in Vivado HLS.
-Co-simulation waveforms are enhanced to clearly display DATAFLOW transaction views.
-New DRCs added to the Vivado HLS GUI DRC tab to expedite timing closure and strengthen pragma checks.

HOMEPAGE

https://www.xilinx.com/

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