Communication Series P1 : Uart, Spi And I2C In Verilog
Published 11/2023
MP4 | Video: h264, 1920x1080 | Audio: AAC, 44.1 KHz
Language: English | Size: 2.11 GB | Duration: 6h 51m

A Step-by-Step Guide[/center]

What you'll learn
Essential principles of UART, SPI, and I2C.
Implementation of UART 16550A, PMOD DA4.
Different Modes of SPI, Daisy Chain Configuration of SPI.
Bit Banging
Requirements
Fundamentals of Digital Electronics, Verilog.
Description
This comprehensive course is meticulously designed to cater to a broad audience, ranging from beginners who are just stepping into the world of digital design and hardware description languages (HDLs) to experienced FPGA/ASIC developers looking to deepen their expertise. The central aim of this course is to equip participants with a thorough mastery of digital communication interfaces, employing Verilog as the primary tool. Regardless of your prior experience in the field, this course offers something valuable. Beginners will find a structured and gradual introduction to the complex world of digital communication interfaces and Verilog. The course spans a comprehensive curriculum that encompasses three fundamental digital communication protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver-Transmitter (UART), and Inter-Integrated Circuit (I2C). Each of these protocols plays a critical role in modern electronics and embedded systems, and mastering them is vital for both aspiring and experienced engineers.In summary, this course is a transformative journey that welcomes participants at all skill levels into the world of digital communication interfaces and Verilog. It equips you with the skills, knowledge, and confidence needed to excel in the dynamic and ever-evolving field of digital design and embedded systems. Whether you're taking your first steps or seeking to advance your career, this course provides a robust foundation for your success.
Overview
Section 1: UART
Lecture 1 Simple UART TX
Lecture 2 Simple UART RX
Lecture 3 Simple UART TB
Lecture 4 Design Code
Lecture 5 TB Code
Lecture 6 UART 16550A Overview
Lecture 7 UART 16550 : FIFO P1
Lecture 8 UART 16550 : FIFO P2
Lecture 9 UART 16550 : FIFO P3
Lecture 10 UART 16550 : FIFO P4
Lecture 11 FIFO TB
Lecture 12 Design Code
Lecture 13 Testbench Code
Lecture 14 TUART 16550 TX : Understanding Oversampling in Baud Generator
Lecture 15 UART 16550 TX : LCR (Line Control Register)
Lecture 16 UART 16550 TX : Stop bits
Lecture 17 UART 16550 TX : TX Logic
Lecture 18 UART 16550 TX : TX TB
Lecture 19 Design Code
Lecture 20 TB Code
Lecture 21 UART 16550 RX : RX Logic
Lecture 22 UART 16550 RX : RX TB
Lecture 23 Design Code
Lecture 24 TB Code
Lecture 25 UART 16550 Registers : Overview
Lecture 26 UART 16550 Registers : THR and RBR
Lecture 27 UART 16550 Registers : Divisor Latch
Lecture 28 UART 16550 Registers : FCR and LCR
Lecture 29 UART 16550 Registers : LSR
Lecture 30 UART 16550 Registers : TB
Lecture 31 Design Code
Lecture 32 TB Code
Lecture 33 Complete Design
Lecture 34 TX testbench
Lecture 35 Design Code
Lecture 36 TB Code
Section 2: SPI
Lecture 37 SPI protocol without different mode
Lecture 38 SPI Master P1
Lecture 39 SPI Master P2
Lecture 40 SPI Master P3
Lecture 41 Code
Lecture 42 SPI Slave P1
Lecture 43 SPI Slave P2
Lecture 44 Code
Lecture 45 Alternate Implementation
Lecture 46 Code
Lecture 47 Understanding CPOL behavior
Lecture 48 Implementation
Lecture 49 Code
Lecture 50 Understanding CPHA
Lecture 51 Understanding SPI Modes with different CPOL and CPHA
Lecture 52 Working with CPHA Master
Lecture 53 Master TB
Lecture 54 Code
Lecture 55 Working with CPHA Slave
Lecture 56 Code
Lecture 57 Digilent PMOD DA4 (Analog Devices AD5628) : Understanding Specifications
Lecture 58 Digilent PMOD DA4 (Analog Devices AD5628) : Master Design
Lecture 59 Digilent PMOD DA4 (Analog Devices AD5628) : TB
Lecture 60 Design Code
Lecture 61 TB Code
Lecture 62 Daisy Chain Configuration
Lecture 63 Master
Lecture 64 Slave
Lecture 65 Testbench
Lecture 66 Design Code
Lecture 67 TB Code
Lecture 68 One Notes
Section 3: I2C
Lecture 69 Overview
Lecture 70 Understanding I2C Open Drain Interface
Lecture 71 Start and Stop Conditions
Lecture 72 I2C Write and Read Transactions
Lecture 73 I2C Master FSM without Clock Stretch
Lecture 74 I2C Master without clock stretch
Lecture 75 Master TB
Lecture 76 Design Code
Lecture 77 TB Code
Lecture 78 I2C Slave without clock stretch
Lecture 79 Testbench for top
Lecture 80 Design Code
Lecture 81 TB Code
Lecture 82 Bit Banging
Lecture 83 Understanding Clock Stretching
Lecture 84 Implementation of Master
Lecture 85 Implementation of Slave
Lecture 86 Design Code
Lecture 87 TB Code
A VLSI engineer is interested in constructing the foundational elements of the standard communication interfaces frequently utilized in FPGA systems.

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