Cadence IC6.1.7 ISR22 Virtuoso | 5.3 Gb
Cadence Design Systems, Inc. has launched Cadence IC6.1.7 ISR22 Virtuoso, a formal, streamlined and automated co-design and verification flow between the Cadence Virtuoso platform and Allegro and Sigrity technologies. This higher level of integration enables engineers to design concurrently across the chip, package and board.
By automating what has until now been a manual process, the Virtuoso System Design Platform minimizes errors and can reduce layout versus schematic (LVS) time between IC and package from days to minutes.
Until now, advances in silicon technology have been sufficient for continued improvement in microelectronics products. Given the complexity of today's chips, packages and boards, ICs based on both silicon and non-silicon materials are now required to design optimal high-performance systems. As a result, this trend is driving the need for engineers to integrate multiple heterogeneous technologies in a single product, affecting the performance and functionality of ICs and introducing a new set of challenges for semiconductor companies. To address these challenges, Cadence has developed a novel, cross-platform solution that streamlines and automates the design of a package or module featuring off-chip devices and multiple ICs based on differing process design kits (PDKs).
The Virtuoso System Design Platform allows IC designers to easily include system-level layout parasitics in the IC verification flow, enabling time savings by combining package/board layout connectivity data with the IC layout parasitic electrical model. The resulting automatically generated "system-aware" schematic can then be easily used to create a testbench for final circuit-level simulation. Until now, designers were only able to make changes after time-consuming manual checks involving spreadsheets and other ad hoc/manual methods, which can take days. By automating this entire flow, the Virtuoso System Design Platform eliminates the highly manual and error-prone process of integrating system-level layout parasitic models back into the IC designer's flow, reducing days of work to mere minutes.
1969824 ADE Assembler dspf_include additional arguments get broken in netlisting
1963701 AutoVia creates a via with offset
1962644 stripe insertion needs to honor pre-existing same-net stripe shapes
1962385 streamin wipes out cds.lib
1961783 EMIR solver keeps switching back to direct method in IC6.1.7 ISR20
1961655 Backannotation of DC operating point slows down schematic operations
1961531 VDR should not label dummy instances that do not have a value in the dataset
1960970 AutoVia should consider center-center spacing in via arrays
1959810 VDR labels incorrect on dummy instances
1959777 Create wire drops a via with wrong cut
1959165 Improve UNL error message: Error encountered while registering text designs in the configuration.
1956904 Layout XL check warning provides incorrect syntax for SKILL code solution
1956703 AutoVia does not toggle via mask color when minSideSpacing violation occurs
1955729 Zooming-in on schematic with DC operating point annotation is slow, specific to config view testbench
1955473 Worst Case Corner changes model file order
1955296 Via device size has changed in ICADV12.3 ISR19
1954846 CDLout ICADV12.3 ISR20: Empty subckt not printed if CDF namePrefix is nil
1954730 Layer name appears twice in set member alignment and spacing option
1954335 schematic editing becomes slow after annotating dc operating points
1953455 Poor schematic editor performance if simulation results are annotated
1952868 Allow merging of custom constraint definitions
1952653 Size Over Corners behavior is different from documented flow
1952382 Tech File Field Issues
1951743 Cannot Description rfEdgePhaseNoise from Direct Description with the sweep
1951663 LSF C++ API message "The job was preempted by the License Scheduler" incorrectly reported as a disk space issue in ADE
1951646 Zooming-in on schematic with DC operating point annotation is slow, specific to config view testbench
1951223 Analog options form has two options that are not explicitly placed on a page
1951185 ADE Assembler/ADE Explorer - "Description all" option does not Description all corners for scalars
1950379 Detail routing gets very slow due to minLargeNeighborViaArrayCutSpacing rule
1949243 Very long simulation preparation time (freeze) of maestro in case of big maestro db size and large run plan
1949121 Virtuoso crash with dbLayerNoHoles
1948716 Effect of Target Yield for WCD and SSS
1948500 Autoplacer not snapping stdcells to grid
1948232 Stretch command displays inexistent shape with hexagonal ends and the pathSeg is stretched (ICADV12.3 ISR20)
1948048 Active setup is lost when OCEAN XL is stopped during run
1948046 For Multiple Runs' option should not appear in ADE Explorer job policy setup form
1947690 With ADE Explorer, in corner simulation Edge Phase Noise gives error
1947566 Edge Phase Noise Descriptionting from ADE Assembler Fails
1946393 ICRP jobs do not end after AMS simulation is complete
1946185 eadModelGen fails to generate an eadTechFile
1946020 Problem with Abstract Smart Display. Color-coding does not work as it did in previous ISR
1946011 Grid Pattern Editor "Text" fields. Copy/Paste from XLS fails for Orientation field, works for Pattern field
1946010 Pattern preset User defined pattern is lost anytime a new topology is chosen
1945651 After running an AMS simulation in ADE Assembler, the ICRP jobs remain stuck
1945510 Cells are not placed correctly in rows
1945499 Analog refine with adjust prBoundary creating shorts
1945307 Cannot Description rfEdgePhaseNoise from Calculator or ADE XL outputs, only via direct Description
1944539 Memory Estimation fails giving WARNING (ASSEMBLER-2331): 0 is an invalid variable value
1944361 Probe from top level got different result than probe from bottom level
1944314 ciCacheNeedRefresh() shows changed behavior on zero size constraint view in IC6.1.7 ISR20 as compared to IC6.1.7 ISR8
1943810 environmentOptions file contains (envOpts liqQueueToken) which prevents "spectre.envOpts" "licQueueToken" from working
1943620 Sensitivity Analysis DC Sim to get the mismatch parameters ignores the global variables
1943304 VSDP - Schematic to SiP - PXL failure - CDF Params
1942691 graph parameters display wrong when Descriptionting scalars
1942438 Inclusion of an encrypted IP block from a third party vendor gives an internal error - visadev: *F,INTERR
1942388 Custom Digital Placer does not drop tap cells on rows where component types are split
1941346 Loading a schematic net probe of a non-existent netname causes a hard SKILL error
1940324 power hookup flow: crash starting 6/14 mainline build
1940152 Schematic zoom/pan slow when DC OP is annotated
1938430 Wrong resistance path and results for diagonal wire extraction
1937881 Warning message when executing diff-pair routing
1937747 ICRP process not released upon completion of adexl corners job
1937662 Deleting dummies from GPE text editor causes GPE table to be empty
1937503 AMS UNL segmentation fault in hnlSfProcessInstMasterCells on s schematic Pcell
1937445 Virtuoso fails to run accurate k sigma corners with VVO
1936447 When Descriptionting Scalars, Column Titles on Left side of Waveform Window Do Not Align with Column Content
1936307 Scroll bar position gets reset to the left when using hiReportSelectItems to set the choice in ReportField
1936083 leYankFigs creates new rows in hierarchical read-only cells
1935871 Incorrect markers are generated when checking DRD with the minSameNetSpacing constraint
1934542 VSR is not honoring Prefer Violations to Open
1934244 Pnoise noise type change from Spectre 16.1 to Spectre 17.1: how to migrate ADE tests
1933457 Allow jumping when adjacent layers cannot cross each other
1933399 Virtuoso crashes when importing local csv variable into ADE Explorer
1933203 Si.log contains *Error* eval: undefined function - uiLoadTrigger
1933195 Virtuoso crashes while changing instance binding in HED
1933149 In ICADV12.3 ISR19, auCdlPrintEmptySUBCKT uses incorrect information from CDF termOrder
1933074 VAR expression in Additional Arguments table cannot be processed correctly
1932965 AnalogLib 'isource' element: Does not have option to set 'modulation' to 'pam4'
1931706 AMS simulation from ADE XL/ADE Explorer/ADE Assembler errors out when using SNA (substrate noise) netlist procedure
1931024 loading ael functions in libinit.il for Quantus QRC
1928991 Virtuoso crashes when opening a config view
1928656 Using envSetVal in .cdsinit to append Additional Arguments Field does not work for a state saved before IC6.1.7 ISR17
1927439 When a VHDL file is specified in External Sources tab, VHDL toolbox displays a warning during netlist generation
1926615 SystemVerilog netlister fails to produce correct netlist when ports of type unpacked array are used on symbols
1925802 Virtuoso keeps reading in the simulation directory and results database when showing dcOp annotations in schematic
1923089 Virtuoso crashes when abeLayerToHilightSet works with non-orthogonal data
1922817 modgen routing leaves net connection open
1922225 VSDP includes model file for each instance of the same component
1921877 Cannot find the hotspot of Reff
1921528 CPH does not consider the 'initIOPinPurposeNames' env var
1921526 able to toggle ADE Outputs checked/unchecked radio button down in the hierarchy of schematic
1918922 Virtuoso crashes when leHiCreateRect() is used with IC6.1.7 ISR18
1918800 Unable to Description corners as sweep variables
1916801 Support to print parameters on the instance line instead of under defparam in AMS
1915120 Via justification changes when stretching wire
1914677 EAD does not run when the schematic view is not named 'schematic'
1914519 hiHyperTextReplace with "\n" works in IC6.1.6, but not in IC6.1.7
1913417 MSPS API slowing down schematic redraw when results annotated
1912866 ncelab: *E,CUVWLP (./netlist.vams,21007|21): Too many module port connections
1912143 REGRESSION BF: Trace Legend Shows incorrect values of variables if a scaler expression is Descriptionted across corners
1910808 NC Verilog netlist expands buses with non-existing index
1910757 In the extracted view flow, diode AREA=0 in extview.tmp, but is changed to diode AREA=CDF default value in the extracted view
1910064 auCDL netlister runtime improvement
1909979 No simulation results generated for EAD when schematic view name is different from 'schematic'
1909020 Placer reports incorrect overlap in log
1908437 performance delay in 'zoom in' when the 'Annotations > DC operating points' options is selected
1907548 Virtuoso Layout crashes in IC6.1.7 ISR17
1907020 XOASIS IN fails to read an OASIS file with a large compressed block
1906860 When the 'Selected area' option is selected and title block is present in the schematic, an image exported from Virtuoso Schematic Editor contains a cross marker or line
1906362 Cannot Description Edge Phase Noise in ADE XL or ADE Assembler
1906085 AMS in maestro : Provide an API to add additional arguments in the Simulator Options form for specific tests
1905603 In a config view testbench, zooming-in on schematic with DC operating point annotation is slow
1905405 When running AMS simulation, schematic Pcell binding for a cell with multiple schematics gives E,EXNEUS error
1900191 Virtuoso crashes when binding in HED Tree View
1900165 Improve the netlister.log file error messages when netlisting fails due to compilation of design
1895358 "auCdl netlisting is unable to extract the correct multiplicity value when cdlNetlistType = 'fnl or when netlisting 'flat'
1894553 oaScan is unable to repair a database with a corrupted busNetDef
1892199 onTrack constraint not being generated for some design views
1881080 Cannot read database because the disk TOC of data type 'vectorInstDef' is corrupted
1876515 Saving while in partial read can lead to TOC inconsistencies if db shrinks after open
1858410 In ICADV12.3 ISR16, VSR reports pins that are not accessible due to Wire Assistant layer/via settings
1843719 VLS crashes during abeLayerTouch (with only octilinear shapes in the cell)
1843693 Virtuoso crashes when running abe SKILL functions.
1842857 VSR routability check should report m2 pin with blockage
1840651 hiExportImage creates spurious lines
1835562 Corrupted diskTOC encountered while copying data
1825296 auCdl introducing connectivity bug
1809762 Voltus-Fi: Generate separate reports for short-peak/long-peak multiple time windows
1809755 Voltus-Fi: If skip_sim is selected, fin-check command does not pick .measure file from specified simulation directory
1805400 shielding should use the tieShield constraint set on per shield constraint group basis
1775956 Verilog out: WARNING (VLOGNET-184) message should have more details to debug the issue
1697048 Unnecessary flight-lines are exported
About Cadence Virtuoso System Design Platform. The Cadence Virtuoso System Design Platform links two world-class Cadence technologies-custom IC design and package/PCB design/analysis-creating a holistic methodology that automates and streamlines the design and verification flow for multi-die heterogeneous systems.
Leveraging the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment, it provides a single platform for IC-and package/system-level design capture, analysis, and verification. In addition, the Virtuoso System Design Platform provides an automated bidirectional interface with the Cadence SiP-level implementation environment and Sigrity PowerSI 3DEM Extraction Option.
The Virtuoso System Design Platform allows IC designers to easily include system-level layout parasitics in the IC verification flow, enabling time savings by combining package/board layout connectivity data with the IC layout parasitic electrical model. The automatically generated "system-aware" schematic that results can then be easily used to create a testbench for final circuit-level simulation. The Virtuoso System Design Platform automates this entire flow, eliminating the highly manual and error-prone process of integrating system-level layout parasitic models back into the IC designer's flow.
Integrated Heterogeneous Devices
Many of today's analog, RF, and mixed-signal designs require the integration of multiple ICs across varying substrate technologies to achieve required performance goals. The integration of heterogeneous devices allows designers to achieve results that can't easily be duplicated using a monolithic IC (SoC) design approach. At the same time, heterogeneous integration introduces a whole new set of challenges for today's designers.
System in a package (SiP) is one of the most common methods of integrating mixed technologies into a single design. This approach requires seamless integration between the IC and package substrate design teams and an integrated tool flow. The Virtuoso System Design Platform addresses these challenges with a novel, cross-platform solution that streamlines and automates the design of a package/module featuring off-chip devices and multiple ICs based on differing process design kits (PDKs).
Standalone Software Shipped with IC6.1.7:
- Virtuoso Power System L (IC6.1.7)
- Voltus-Fi Custom Power Integrity Solution XL IC6.1.7
- Dracula Design Rule Checker (4.9)
- Dracula Layout Vs. Schematic Verifier (4.9)
- Dracula Parasitic Extractor(4.9)
- Dracula Physical Verification Suite(4.9)
- Dracula Physical Verification and Extraction Suite (4.9)
- Virtuoso Chip Assembly Router (11.3)
Cadence Product Releases Compatible with IC6.1.7
Spectre Circuit Simulators..............................(SPECTRE 17.10.307)
Pegasus/Physical Verification System....................(PEGASUS 18.20.000)
Assura Physical Verification............................(ASSURA 04.15.115)
XCELIUM.................................................(XCELIUMMAIN 18.03.008)
Conformal...............................................(CONFRML 18.10.100)
Innovus.................................................(INNOVUS 18.10.000)
Manufacturability and Variability Sign-off .............(MVS 17.23.000)
Extraction Tools (QRC/Quantus QRC)......................(EXT 18.11.000)
Allegro Sigrity.........................................(SIG 17.00.010)
Silicon-Package-Board Co-Design.........................(SPB 17.20.043)
Watch an RF demo showing the extraction of an inductor from layout and the impact on circuit simulation of a VCO. The Cadence Virtuoso RF Solution improves design cycle productivity, reducing errors in manufacturing and accounting for the electrical and physical effects within a single environment across IC, package, and board design. Its bidirectional interface integrates with the Cadence SiP-level implementation environment, Sigrity PowerSI 3DEM Extraction Option finite element engine, and NI AWR Design Environment platform's AXIEM 3D planar EM software to automate hours of manual work in RFIC and RF Module designs.
About Cadence. Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company's System Design Enablement strategy helps customers develop differentiated products-from chips to boards to systems-in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
Product: Cadence Virtuoso System Design Platform
Version: IC6.1.7 ISR22*
Supported Architectures: x86
Website Home Page :
www.cadence.com
Language: english
System Requirements: Linux
Supported Operating Systems: RHEL 5, RHEL 6, SLES 11.0
Size: 5.3 Gb
* The IC6.1.7 ISR stream is a cumulative stream of all hotfixes that are submitted after the base release.
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